Millions of individual transistors are coupled together to form very large-scale integrated (VLSI) circuits, such as microprocessors, memories, and application specific integrated circuits (IC's). Presently, the most advanced IC's are made up of approximately millions of transistors, such as metal oxide semiconductor (MOS) field effect transistors. In order to continue to increase the complexity and computational power of future integrated circuits, more transistors must be packed into a single IC (i.e., transistor density must increase). Unfortunately, the structure and method of fabrication of conventional MOS transistors cannot be simply “scaled down” to produce smaller transistors for higher density integration.
The structure of a conventional MOS transistor 100 is shown in FIG. 1. Transistor 100 comprises a gate electrode 102, typically polysilicon, formed on a gate dielectric layer 104 which in turn is formed on a silicon (Si) substrate 106. A pair of source/drain extensions or tip regions 110 are formed in the top surface of substrate 106 in alignment with outside edges of gate electrode 102. Tip regions 110 are typically formed by well-known ion implantation techniques and extend beneath gate electrode 102. Formed adjacent to opposite sides of gate electrode 102 and over tip regions 110 are a pair of sidewall spacers 108. A pair of source/drain contact regions 120 are then formed, by ion implantation, in substrate 106 substantially in alignment with the outside edges of sidewall spacers 108.
In complementary metal oxide semiconductor (CMOS) fabrication, the silicon based substrate may be replaced to produce a “strained” transistor. Strained Si technology enables improvements in CMOS performance and functionality via replacement of the bulk, cubic-crystal Si substrate with a Si substrate that contains a tetragonally distorted, biaxially strained Si thin layer at the surface. Due to changes in its crystalline structure (i.e. its symmetry is different due to its strain state), the strained Si layer has electronic properties that may be superior to those of bulk Si. Specifically, the strained Si layer has greater electron and hole mobilities, which translate into greater drive current capabilities for CMOS transistors. Growing a Si layer on a silicon germanium (SiGe) layer, which has a larger lattice constant than Si, generates the strained Si heterostructure. The amount of strain that may be imparted on the Si layer is determined by the amount of Ge content in the underlying SiGe layer. Inconsistencies in the SiGe layer may result in variations in the strain imposed by SiGe growth. For example, a substrate region that is etched for SiGe growth may possess significant variability and be isotropic in nature.